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CMX625
ISDN TA POTS Interface
D/625/2 July 2001 Advance Information
Features
* SPM and Ringing Voltage Generators * Integrated DTMF Decoder/Encoder * V.23/Bell 202 FSK/Tone Generator * Selectable A-Law/-Law PCM Codec * IOM-2 Interface Terminal Mode and Non-Terminal Mode (Line Card Mode)
Applications
* ISDN NTUs with Analogue Ports * ISDN Line Cards * Wireless Local Loop Termination Cards * ISDN Terminals with Additional POTS Ports * PC based ISDN Cards with Telephone Ports * Billing/SPM Systems
IOM is a trademark of Siemens AG
1.1
Brief Description
The CMX625 is an integrated telecom tone generator, DTMF encoder/decoder and PCM Codec-Filter designed for ISDN interfaces, Wireless Local Loop and other digitised speech systems. The tone generator covers a wide range of pre-programmed tones used in analogue phone systems. Three outputs are provided: Ringing signals, In-band tones or FSK data, and 12kHz/16kHz Subscriber Metering pulses. The PCM Codec-Filter performs voice digitisation and reconstruction and incorporates band limiting and smoothing with selectable A-law or -law companding following ITU-T recommendation G.711. The DTMF decoder presents the serial bus interface with the DTMF dialling information received from the telephone user and the tone generator sends the appropriate DTMF tones to this POTS interface. Other tone standards supported are: Fax and Modem `answer' and `originate', ITU-T `R1' and `R2' signals, dual tones for CIDCW and 'On-Hook' signalling systems and sufficient tones for simple melody generation. The IOM -2 (ISDN Oriented Modular revision 2) industry standard serial bus provides the digital interface to other telecommunications ICs and supports both Terminal and non-Terminal (or Line Card) modes. The CMX625 is compatible with the CMX635 ISDN Subscriber Processor and can be used to provide the additional POTS port. It is available in both DIP and SSOP packages.
(R)
2001 Consumer Microcircuits Limited
ISDN TA POTS Interface
CMX625
CONTENTS Section 1.1 1.2 1.3 1.4 1.5 Page Brief Description ..................................................................................... 1 Block Diagram ......................................................................................... 3 Signal List ................................................................................................ 4 External Components ............................................................................. 6 General Description ................................................................................ 7 1.5.1 IOMTM-2 Serial Bus Interface ..................................................... 7 1.5.2 Terminal Mode (TE).................................................................... 8 1.5.3 Non-Terminal Mode (non-TE) ................................................. 10 1.5.4 Monitor Channel Handshake Protocol................................... 11 1.5.5 Monitor Channel Identification Command ............................ 13 1.5.6 PCM Codec-Filter ..................................................................... 13 1.5.7 Rx Input Amplifier .................................................................... 14 1.5.8 Tx Output Buffer ...................................................................... 14 1.5.9 Tone/FSK Encoder and Tone Encoder .................................. 14 1.5.10 SPM Generator ......................................................................... 17 1.5.11 Transmit Signal Control .......................................................... 17 1.5.12 Tx UART .................................................................................... 18 1.5.13 DTMF Tone Decoder ................................................................ 19 1.5.14 Register Set .............................................................................. 20 1.5.15 Programming the CMX625 ...................................................... 20 1.5.16 Glossary.................................................................................... 22 Application Notes.................................................................................. 23 1.6.1 Telecom Tones ......................................................................... 23 Performance Specification................................................................... 27 1.7.1 Electrical Performance ............................................................ 27 1.7.2 Packaging ................................................................................. 33
1.6
1.7
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1.2
ISDN TA POTS Interface
RESET
FSC TE/NTE SA0 SA1 SA2 DS
DCL
DD
DU
IRQN
Block Diagram
IOM(R)-2 Serial Bus Interface SETUP & MODE Registers STATUS Register PCM Codec Registers Interrupt Generator
2001 Consumer Microcircuits Limited
FSK / TONES Tx Registers
Rx Input Amplifier DTMF Tone Decoder STATUS & IRQ BUS SPM Generator SPM
RXN
RXP
Enable
RXO Tx Output Buffer ROM STATUS & IRQ Tone Encoder Tx UART Tone / FSK Encoder
Vbias Enable
TXN TXO TXON
Figure 1 Block Diagram
3
VDD
VBIAS
Tx Signal Control
RING TONEFSK
VSS
PCM ADC A-law / -law
Analogue Loopback
PCM DAC A-law / -law
DAC OUT
D/625/2
CMX625
ISDN TA POTS Interface
CMX625
1.3
Signal List
CMX625 D5/P4 Pin No. 1 Signal Name FSC Type I/P The IOM-2 Frame Synchronisation Clock. This is an 8kHz clock indicating the start of the frame. FSC is generated by the upstream device. See section 1.5.1, 1.5.2 and 1.5.3. The IOM-2 Data Clock. It is used to clock data on and off the bus and operates at 1.536MHz for Terminal mode (TE) or 4.096MHz for non-Terminal mode (non-TE or Line Card mode). DCL is generated by the upstream device. When the bus is deactivated, DCL is held in a low state. See section 1.5.1, 1.5.2 and 1.5.3. The IOM-2 Data Downstream, receives data from the network. When the bus is deactivated or when data is not being transmitted, DD is high impedance. The IC Channel Bus Reversal (TE mode only) allows IC1 and IC2 data to be transmitted on the DD pin. See section 1.5.1, 1.5.2, 1.5.3 and 1.5.6. An external pull-up resistor is required. The IOM-2 Data Upstream, transmits data to the network. When the bus is deactivated or when data is not being transmitted, DU is high impedance. The IC Channel Bus Reversal (TE mode only) allows IC1 and IC2 data to be received on the DU pin. See section 1.5.1, 1.5.2, 1.5.3 and 1.5.6. An external pull-up resistor is required. The IOM-2 two modes of operation: TE = 0 selects Terminal mode. NTE = 1 selects Non-Terminal mode or Line Card mode. See section 1.5.1, 1.5.2 and 1.5.3. ) ) ) ) The IOM-2 Slot Address, provides one of 8 unique addresses. It allows the device to be individually addressed when more than one device is connected to the IOM-2 bus. See section 1.5.2 and 1.5.3. Description
2
DCL
I/P
3
DD
BI
4
DU
BI
5
TE/NTE
I/P
6 7 8 9
SA0 SA1 SA2 DS
I/P I/P I/P I/P
The IOM-2 Device Select pin (NTE mode only). Allows two CMX625 devices sharing a Slot Address to be individually addressed. DS = 0 selects device one. DS = 1 selects device two. See section 1.5.2 and 1.5.3. The external reset pin clears all the registers. (RESET=1) A `wire-Orable' output Interrupt Request. This output is pulled down to VSS when active and is high impedance when inactive. An external pull-up resistor is required.
10 11
RESET IRQN
I/P O/P
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CMX625
CMX625 D5/P4 Pin No. 12 13 14 15 16
Signal Name VSS RXP RXN RXO VBIAS Type Power I/P I/P O/P O/P
Description
The negative supply rail (ground). The non-inverting input of the receive op-amp. The inverting input of the receive op-amp. The output of the receive op-amp. An internally generated bias voltage of VDD/2, except when the device has been reset, VBIAS will discharge to VSS. It should be decoupled to VSS by a capacitor mounted close to the device pins. The sinewave output of the Tones and FSK signal generators. The output of the buffer amplifier. The inverting input to the buffer amplifier. The inverted output of the buffer amplifier. The output from the digital-to-analogue converter. The square, trapezoidal and sinusoidal wave output from the Ringing Signal Generator. The sinewave output of the SPM signal generator. The positive supply rail. Levels and thresholds within the device are proportional to this voltage. It should be decoupled to VSS by a capacitor mounted close to the device pins.
17 18 19 20 21 22 23 24
TONEFSK TXO TXN TXON DAC OUT RING SPM VDD
O/P O/P I/P O/P O/P O/P O/P Power
Notes:
I/P O/P BI N/C
= = = =
Input Output Bi-directional No (external) Connection
This device is capable of detecting and decoding small amplitude signals. To achieve this VDD and VBIAS decoupling and protecting the receive path from extraneous in-band signals are very important. It is recommended that the printed circuit board is laid out with a ground plane in the CMX625 area to provide a low impedance connection between the VSS pin and the VDD and VBIAS decoupling capacitors.
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1.4
External Components
VDD
FSC
VDD R6 R7
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD
SPM RING DAC OUT TXON TXN TXO TONEFSK VBIAS RXO RXN RXP
VBIAS R2 C1 R3 C4 C3 Rx In VSS C5 R4 R5 C6 Tx In VSS C2
DCL DD DU TE/NTE SA0 SA1 SA2 DS
IOM -2 Bus Interface
TM
CMX625
VDD R1
RESET IRQN
VSS
VSS
Figure 2 Recommended External Components R1, R4 R2, R3 R5 R6, R7 100k 110k 56k Note 2 C1, C2 C3 C4, C5 C6 1.0F 100nF 220pF 22nF
Resistor 1%, capacitors 5% unless otherwise stated. Note: 1. The recommended component values, C3 to C6 and R2 to R5 and tolerances are essential to meet the ITU-T Recommendation G.172 filter specification. See figure 12. 2. R6, R7 = 750 with 5V supply. R6, R7 = 470 with 3.3V supply.
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D/625/2
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CMX625
1.5
General Description
The CMX625 is a telecom tone generator, DTMF tone encoder/decoder and PCM Codec-Filter for ISDN interfaces. The PCM Codec-Filter performs voice digitisation and reconstruction and incorporates encoder bandpass and decoder lowpass filters with pre and post-filtering with selectable A-law and -law companding following ITU-T recommendation G.711. The device has separate output ports for the four different classes of signals encoded. These include Ringing signals, In-band tones or FSK data at 1200bps, high frequency metering pulses (SPM tones) and DAC signals. It has a transmit level attenuator for In-band tones or FSK data and an envelope control for SPM tones. The device also has an uncommitted Tx output buffer for filtering and impedance matching. The functions are controlled via an IOM-2 serial bus interface. Frequency and timing accuracy of the CMX625 is supplied by the Data Clock (DCL) of the IOM-2 serial bus interface. If the bus is deactivated, DCL is held in a low state. The CMX625 can be reset externally by driving the RESET pin low. It resets all the internal register bits and ensures that the interface always starts from a known state. The device can also be reset by issuing a RESET command. See section 1.5.14. Commands to enable and disable individual functions are also shown in this section. Approximately 50ms should be allowed for the Tx dc level to settle at VBIAS before enabling the Tx functions (set bit 6 of the MODE Register to `1') after the CMX625 has been reset.
1.5.1
IOM-2 Serial Bus Interface
(R)
The IOM -2 (ISDN Oriented Modular revision 2) is an industry standard serial bus for interconnecting telecommunications IC's. (Refer to the IOM-2 Interface Reference Guide, Industry Standard Bus by (R) Advanced Micro Devices). The bus is an evolution of the IOM interface and is also known as the GCI (General Circuit Interface). The IOM-2 bus provides a symmetrical full duplex communication link, containing user data, control/programming and status channels. There are two basic modes of operation known as Terminal mode (TE mode) and non-Terminal mode (non-TE or Line Card mode). These modes differ in the frame structure and data rate. The frame rate remains at 8kHz for each mode. The CMX625 acts as a timing and control slave to the upstream device. The various channels are time multiplexed over a basic four wire serial interface, namely FSC, DCL, DD and DU. Frames are delimited by an 8kHz Frame Synchronisation Clock (FSC) which is generated by the upstream device. The Data Clock (DCL) clocks data on and off the bus and runs at either 1.536MHz (TE mode) or 4.096MHz (non-TE mode). It is always generated by the upstream device. Data Downstream (DD) receives data from the network. Data Upstream (DU) transmits data to the network. When the bus is deactivated or when data is not being transmitted, DD and DU is held in a high impedance state. The DD and DU bus are driven by open drain transistors such that all DD's and DU's can be connected together. Bus reversal (in TE mode) allows the DD and DU pins to be both inputs and outputs in the IC1 and IC2 channels. It allows use of the CMX625 with post processing devices that are IOM-2 compliant. When other devices are connected to the IOM-2 bus the three Slot Address pins (SA0, SA1 and SA2) provide a unique address, allowing the CMX625 to be individually addressed. The Device Select pin (DS) allows two CMX625 devices sharing a slot address to be individually addressed in non-TE mode. The remote digital IOM loopback is enabled when bit 3 of the IOM CONTROL Register is set to `1'. This loops back the data arriving on the IOM-2 bus and sends it back again. Unused bits in the frame structure are ignored if not required by the CMX625. These bits will be set to '1' when the frame is transmitted upstream.
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CMX625
1.5.2
Terminal Mode (TE)
Terminal mode (TE) frame structure consists of 3 channels of 4 bytes each repeated at 8kHz, i.e. 96 bits in 125s or a data rate of 768kbps. The Data Clock (DCL) operates at twice the data rate, i.e. 1.536MHz. Figure 3 shows the TE mode frame structure.
125s FSC
DCL
DU/DD
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 0
B1
B2
M S B
MON0
L S B
D
C/I0 R X
MM
CHANNEL 1
IC1
IC2
MON1
C/I1
MM RX
CHANNEL 2
Not Used
Not Used
Not Used
TIC
FSC = 8kHz DCL = 1.536MHz DD, DU = 768kbps Figure 3 Terminal Mode Frame Structure `Channel 0' is used for passing user data (2B+D channels) and controlling (MON0 and C/I0) the Layer 1 transceiver. Only `Channel 1' is used by the CMX625. `Channel 2' is reserved for D channel arbitration. The 12 byte frame contains the following channels: (i) The `B' channels consist of two 64kbps data channels, labelled B1 and B2, and transfer B channel data to and from the network.
(ii) The `Monitor' channels consist of two programming channels, labelled MON0 and MON1. Each channel consists of 8 bits of data and has two associated pair of handshake bits that control data flow, MX and MR (monitor transmit and receive). The handshake procedure is described in section 1.5.4. The MON1 channel is used for programming and controlling devices attached to the IOM-2 interface. The CMX625 is programmed via the MON1 channel (see section 1.5.15). The MON0 channel is not used. Monitor channel contention is avoided by a "speak when spoken to" system whereby the CMX625 is given a unique address, programmed with the 3 Slot Address pins (SA0 to SA2) and 1 Device Select pin (DS) and only responds when that address is broadcast by the master device (see section 1.5.14). The Monitor channel address byte is shown below:
Bit 7 MON Channel Address Byte 1 Bit 6 Slot Address SA2 Bit 5 Slot Address SA1 Bit 4 Slot Address SA0 Bit 3 Device Select DS Bit 2 0 Bit 1 0 Bit 0 0
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CMX625
The CMX625 cannot initiate MON communication directly in a multi-slave application. Each slave must monitor the MON channel for its unique address in the first byte before processing the following command. Each slave can therefore only drive the DU MON channel when specifically requested to by the master. (iii) The `D' channel consists of two bits providing 16kbps for carrying D channel user data. This channel is not used by the CMX625. (iv) The `Command/Indicate' channels, labelled C/I0 and C/I1, provide real time status information between devices connected via the IOM-2 bus. The C/I0 in channel 0 consists of 4 bits and the C/I1 in channel 1 is 6 bits wide. The C/I0 in channel 0 is not used. The C/I1 channel is shared by all devices on the IOM-2 bus with no mechanism for determining and resolving contention. If multiple slave devices are expected to drive the C/I1 channel then care must be taken to allocate different bits to each device. An example of C/I1 channel usage would be 6 slave devices each allocated one of the 6 C/I1 bits. When a slave requires attention it asserts its own bit, which is detected by the master as a C/I1 value change (generating a processor interrupt). The processor would then initiate MON1 communications with the appropriate slave and service its request. This is an example of one usage, but the C/I1 bits may be used for any real time command/indicate purpose dependent on system design and number of slaves on the IOM-2 bus. The C/I1 Channel Output Control Code is encoded as follows (bits 0, 1 and 2 of the IOM CONTROL Register): C/I1 Channel Output Control Code (IOM Control Register, Bits 2, 1 and 0) 000 001 010 011 100 101 110 111 C/I1 Channel Output Bit Content C/I1 bits 5-0 = all logic `1', i.e. C/I1 output disabled Interrupt Request (logic `0') on C/I1 bit 0 ) Interrupt Request (logic `0') on C/I1 bit 1 ) Interrupt Request (logic `0') on C/I1 bit 2 ) all other bits logic `1' Interrupt Request (logic `0') on C/I1 bit 3 ) Interrupt Request (logic `0') on C/I1 bit 4 ) Interrupt Request (logic `0') on C/I1 bit 5 ) Status Register bits 7-2 on C/I1 bits 5-0
Code `000' is provided to disable drive of the C/I1 channel for use when multiple slaves have completely utilised the C/I1 channel resource. The Interrupt Mask Register settings are ignored and the C/I1 bits are set to logic `1'. For codes `001' to `110' a logic `0' (Interrupt Request) is driven onto the appropriate C/I1 bit when the Status Register bits contain an unmasked logic `1' (set by the Interrupt Mask Register). This allows other devices to use the remaining C/I bits for their own purposes. The master device would use the change of the appropriate C/I bit to initiate a Status Register read from the CMX625. Code `111' and an unmasked Status Register (INTERRUPT MASK bits 2 to 7 are set to `1') allows the most significant 6 bits of the Status Register to be driven onto the C/I1 channel directly for use when the CMX625 is the only slave utilising the C/I channel. If any of the Status bits are masked, by setting the equivalent bit in the mask register to `0', then a logic '0' will be routed to the appropriate C/I1 bit and will not change.
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CMX625
(v) The `Intercommunication Channel' consists of two 64kbps data channels, labelled IC1 and IC2, and provide additional communications paths between devices other than the layer 1 device (data to and from the layer 1 device is transferred over the B channels). (vi) The `TIC' (Terminal IC) bus is used for connecting more than one device to the D and C/I0 channels in Channel 0. The TIC bus is not used by the CMX625. 1.5.3 Non-Terminal Mode (non-TE)
The non-TE mode (Line Card Mode) frame structure consists of up to 8 channels of 4 bytes each repeated at 8kHz, i.e. 256 bits in 125s or a data rate of 2048kbps for 8 channel frames. The Data Clock (DCL) operates at twice the data rate, i.e. 4.096MHz. Figure 4 shows the non-TE mode frame structure.
125s FSC
DCL
DD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH0
DU
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH0
B1
B2
M S B
MONITOR S
B
L
C/I
MM R X for analogue lines
B1
B2
M S B
MONITOR S
B
L
D
C/I
MM R X for ISDN lines
FSC = 8kHz DCL = 4.096MHz DD, DU = 2048kbps Figure 4 Non-Terminal Mode Frame Structure In non-TE mode the IOM-2 bus time multiplexes data, control and status information for up to eight IOM-2 devices or up to 16 Codec-Filters over a single full duplex interface. The frames are subdivided into 8 channels, with one channel being dedicated to each IOM-2 device or pair of Codecs. Each device on the IOM-2 bus is assigned a slot address and only transmits to and receives from that time slot. Pins SA0, SA1 and SA2 on the CMX625 are used to program the Slot Address. Outside the allocated slot the transmit drivers will be set to high impedance to allow other devices to transmit in their own time slot. To allow two CMX625 devices to share the same slot a Device Select pin (DS) is made available. This pin forms part of the Monitor Channel Address Byte along with the Slot Address pins and allows either of the two devices sharing a slot to be individually addressed. See section 1.5.2, part (ii) MON Channel Address Byte. This mechanism allows both the B1 and B2 data from the same time slot to be utilised by different devices.
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CMX625
Each channel consists of the following 4 bytes: (i) (ii) The first two bytes consist of two 64kbps data channels, labelled `B1' and `B2', and transfer B channel data to and from the network. The third byte, labelled `Monitor', is used for programming and controlling devices attached to the IOM-2 interface. The data structure within the monitor channel is not defined and will be device specific. The CMX625 is programmed via the monitor channel (see section 1.5.15).
(iii) In digital applications (ISDN line cards) the fourth byte contains two bits for the 16kbps `D' channel, four `Command/Indicate' (C/I) bits for real time status information and two handshake bits for supporting the handling of the monitor channel, labelled `MR' and `MX' (monitor transmit and receive). The handshake procedure is described in section 1.5.4. In analogue applications (analogue line cards) there is no 'D' channel in the fourth byte so the adjacent C/I channel is increased to 6 bits. The C/I1 channel bits are used in the same way as for Terminal Mode. 1.5.4 Monitor Channel Handshake Protocol
The Monitor channel operates on an event driven basis. While data transfers on the bus take place synchronised to the frame sync, the flow of data is controlled by a handshake procedure using the outgoing MX (monitor transmit) and incoming MR (monitor receive) bits. Data is placed onto the monitor channel and the MX bit is activated. This data will be transmitted repeatedly (once per 8kHz frame) until the transfer is acknowledged (ACK) via the MR bit. The actual data rate is not fixed but is dependent upon the response speed of the transmitter and receiver. The protocol is applicable to both TE and non-TE modes.
MX EOM
Data
Byte 1
Byte 2
Byte 3
Byte n
MR ACK 125s ACK ACK ACK
Figure 5 Monitor Handshake Timing (general case) Figure 5 shows the general case for monitor handshake timing. The first byte of data is placed on the bus and MX is activated (low). MX remains active and the data remains valid until an inactive-to-active transition of MR is received, indicating that the receiver has read the data off the bus. The next byte is placed on the bus after the inactive-to-active transmission of MR, as early as the next frame (there is no limit to the maximum number of frames). At the time that the second byte is transmitted, MX is returned inactive (high) for one frame (MX inactive for more than one frame indicates an End of Message). In response to MX going active (low), MR will be deactivated (high) for one frame (the MX inactive to MR inactive delay can be any number of frames). This procedure is repeated for each additional byte. The transmitter sends an End of Message (EOM), after the last byte of data has been transmitted, by not reactivating MX after deactivating it. The receiver can hold off the transmitter by keeping MR active until the receiver is ready for the next byte. The transmitter will not start the next transmission cycle until MR goes inactive. The transmitter is able to abort a transmission by holding MX inactive (high) for two or more frames, this will generate an interrupt when the INTERRUPT MASK Register bit 3 is unmasked (logic `1') and bit 3 of the Status Register will be set to `1'.
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CMX625
Figure 6 shows the monitor channel handshake procedure.
MX = Monitor Transmit Bit, active low. MR = Monitor Receive Bit, active high. MD = Monitor Data Figure 6 Monitor Channel Handshake Procedure Figure 7 shows the maximum speed case for monitor handshake timing. The transmitter can be designed for a higher data throughput than is provided by the general case. The transmitter can deactivate (high) MX and transmit new data one frame after MR is deactivated. In this way, the transmitter is anticipating that MR will be reactivated one frame after it is deactivated, minimising the delay between bytes. MR being held inactive (high) for two or more frames indicates an abort is being signalled by the receiver.
MX EOM
Data
Byte 1
Byte 2
Byte 3
Byte n
MR ACK ACK ACK ACK
Figure 7 Monitor Handshake Timing (maximum speed case) The abort is a signal from the receiver to the transmitter indicating that data has been missed. The receiver is able to abort a transmission by holding MR inactive (high) for two or more frames in response to MX going active. An abort from the receiver will generate an interrupt when the INTERRUPT MASK Register bit 2 is unmasked (logic `1') and bit 2 of the Status Register will be set to `1'. Figure 8 shows a monitor abort request from the receiver.
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CMX625
MX
EOM
Data
Byte 1
Byte 2
MR
Abort Request
Figure 8 Abort Request from the Receiver 1.5.5 Monitor Channel Identification Command
In order to be able to identify different devices on the IOM-2 bus, an identification command is sent. This allows the software to identify different manufacturer's devices on the bus. The identification sequence is usually done once, when the device is connected for the first time. A device requesting the identity of a connected CMX625 will transmit the following 2 byte command:
st
DD 1 byte nd DD 2 byte
Bit7 1 0
Bit6 SA2 0
Bit5 SA1 0
Bit4 SA0 0
Bit3 DS 0
Bit2 0 0
Bit1 0 0
Bit 0 0 0
The CMX625 responds by transmitting:
st
DU 1 byte nd DU 2 byte
Bit7 1 1
Bit6 SA2 0
Bit5 SA1 0
Bit4 SA0 1
Bit3 DS 1
Bit2 0 0
Bit1 0 0
Bit 0 0 1
Monitor Channel Address Byte Device Identification Byte
SA(2-0) = Slot Address, DS = Device Select (see sections 1.5.2 and 1.5.3). See section 1.5.14 for the Device Identification Register. 1.5.6 PCM Codec-Filter
The PCM Codec-Filter performs voice digitisation and reconstruction and incorporates encoder bandpass and decoder lowpass filters with pre and post-filtering with selectable A-law and -law companding. In each case the coder and decoder process a companded 8-bit PCM word following ITU-T recommendation G.711 for A-law and -law conversion. The encoder bandpass filter and decoder lowpass filter provide passband flatness and stopband rejection according to ITU-T recommendation G.712. The lowpass filter contains the required (Sin X)/X compensation. The overall filter characteristics of the channel are shown in Figure 12. The PCM Codec-Filter block is enabled or disabled by bit 7 of the CODEC CONTROL Register. The companding law is selected by bit 6. When this bit is a `0', A-law companding is selected (used in Europe) and when this bit is a `1', -law is selected (used in the USA and Japan). The PCM Codec Channel routeing is shown in the table below for normal operation and bus reversal. In `normal' operation, bit 4 of the IOM Control Register is set to `0', the data is transmitted on the Data Upstream (DU) pin and received on the Data Downstream (DD) pin. Bits 6 and 7 of the IOM Control Register select whether the data is transmitted or received on the B1, B2, IC1 or IC2 channels of the IOM2 bus. The B1 and B2 channels are available in TE and non-TE mode but the IC1 and IC2 channels are only available in TE mode.
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Codec Channel Input/Output Select IC Channel Bus Reversal Codec Channel Select Codec (IOM Control Register (IOM Control Register, Data Bit 4) Bits 7 and 6) From 0 00 B1, DD Normal 0 01 B2, DD 0 10 IC1, DD 0 11 IC2, DD 1 00 B1, DD Reverse 1 01 B2, DD 1 10 IC1, DU 1 11 IC2, DU
Codec Data To B1, DU B2, DU IC1, DU IC2, DU B1, DU B2, DU IC1, DD IC2, DD
In Terminal mode (TE) it may also be necessary to transmit on the Data Downstream (DD) pin and receive on the Data Upstream (DU) pin during the IC1 and IC2 time slots. This can be achieved by selecting bus reversal and allows use of the CMX625 with post processing devices, such as speech scramblers, that are IOM-2 compliant. Bus Reversal is enabled when bit 4 of the IOM Control Register is set to `1' and programming the appropriate Codec Channel Select bits 6 and 7 of the IOM Control Register. When bus reversal is active, the master device and any other devices capable of bus reversal, are prohibited from broadcasting in the active IC channel. Local analogue codec loopback is enabled when bit 5 of the CODEC CONTROL Register is set to `1'. This internally connects the DAC output to the ADC input (the connection to the Rx Amp is broken). Data is loaded and read via the IOM-2 bus using the channels shown in the above table. 1.5.7 Rx Input Amplifier
This amplifier, with suitable external components, is used for adjusting the received signal to the correct amplitude for the DTMF decoder and the PCM analogue-to-digital converter. See Figure 2 Recommended External Components. 1.5.8 Tx Output Buffer
This buffer is enabled by bit 7 of the SETUP register. With suitable external components it can be used for filtering and impedance matching. See Figure 2 Recommended External Components. 1.5.9 Tone/FSK Encoder and Tone Encoder
These blocks are enabled or disabled by bit 6 of the SETUP register. When bit 5 of the MODE Register is set to `1' then these blocks generate FSK signals as determined by bit 0 of the SETUP Register and the Tx data bits from the UART block, as shown in the table below: SETUP Register Bit 0 0 1 Tone/FSK Generator V23 1200bps FSK Bell 202 1200bps FSK FSK Signal Frequency `0' (Space) 2100Hz 2200Hz FSK Signal Frequency `1' (Mark) 1300Hz 1200Hz
When bit 5 of the MODE Register is set to `0', these blocks generate single or dual tones from the range shown in the tables on the following pages. Bit 6 of the MODE Register is then used to enable or disable the block's output to the Tx Signal Control, RING and TONEFSK outputs. There are four tone fields addressed by bits 0 and 1 of the MODE Register.
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D/625/2
ISDN TA POTS Interface
CMX625
Tone Field 0, MODE Register bit 1 and bit 0 = `0' and `0' respectively. TX TONES Register Bits D7 D6 D5 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 4-7 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency (Hz) 0 = OFF 252.4 268.7 285.3 315.5 330.5 375.2 404.3 468.0 495.8 520.6 548.0 562.8 578.4 595.0 612.5 TX TONES Register Bits D3 D2 D1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0-3 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency (Hz) 0 = OFF * 17.1 * 20.5 * 24.9 * 34.1 * 41.0 * 51.2 262.9 293.6 348.2 392.6 1600 1633 1827 587.2
NOTE: * These outputs are routed to the RING digital output instead of the TONEFSK output. Any single tone output level at TONEFSK output is 0dBm.
Tone Field 1, MODE Register bit 1 and bit 0 = `0' and `1' respectively TX TONES Register Bits 4-7 D7 D6 D5 D4 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Frequency (Hz) 0 = OFF 120 150 154 250 300 350 360 367 375 380 383 400 450 475 480 TX TONES Register Bits 0-3 D3 D2 D1 D0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Frequency (Hz) 0 = OFF 330 416 420 425 433 440 450 460 480 500 600 620 720 930 -
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D/625/2
ISDN TA POTS Interface
CMX625
Tone Field 2, MODE Register bit 1 and bit 0 = `1' and `0' respectively TX TONES Register Bits D7 D6 D5 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 4-7 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency (Hz) 0 = OFF 700 900 1100 1300 1500 1700 950 1400 1800 2130 697 770 852 941 TX TONES Register Bits D3 D2 D1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0-3 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency (Hz) 0 = OFF 700 900 1100 1300 1500 1700 2100 2225 2750 1209 1336 1477 1633
Tone Field 3, MODE Register bit 1 and bit 0 = `1' and `1' respectively TX TONES Register Bits D7 D6 D5 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 4-7 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency (Hz) 0 = OFF 540 660 780 900 1020 1140 1380 1500 1620 1740 1860 1980 TX TONES Register Bits D3 D2 D1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0-3 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency (Hz) 0 = OFF 540 660 780 900 1020 1140 1380 1500 1620 1740 1860 1980 -
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D/625/2
ISDN TA POTS Interface
CMX625
1.5.10 SPM Generator This block operates independently and has its own output pin. It can transmit 12kHz or 16kHz and is controlled by bit 4 of the SETUP Register. Bit 7 of the MODE Register is used to enable or disable this block. The signal has a rise and fall time each of about 4ms. The SPM signal rises from the bias level to 0dBm in 16 steps of 2dB magnitude, and falls from 0dBm to bias level in 16 steps of 2dB magnitude. 1.5.11 Transmit Signal Control This block adjusts the amplitude of the FSK transmit signal output level, the level skew between DTMF tones and the signal routing to the output ports. Output signal levels are proportional to VDD. The nominal output signal levels (at 0dB attenuation and VDD = 5.0V) are: Single Tone Dual Tone (per tone) DTMF High Frequency Tone DTMF Low Frequency Tone FSK Signal 0dBm -3dBm -3dBm -5dBm 0dBm
The level attenuator provides for level adjustment from 0dB to -14dB in -2dB steps. The typical level is determined by bits 2 to 4 of the MODE Register as shown in the table below: MODE Register Bit 4 Bit 3 Bit 2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Signal Level Adjustment (dB) 0 -2 -4 -6 -8 -10 -12 -14
The RING signal is a square, trapezoidal or sinusoidal wave. The square and trapezoidal wave have an amplitude of VDD peak to peak and the sinusoidal wave has an amplitude of 1/2 VDD peak to peak. The trapezoidal ringing waveform has a crest factor (CF) of 1.35. Bits 2 and 3 of the SETUP Register select the waveform type as shown in the table below. SETUP Register Bit 3 Bit 2 0 0 0 1 1 0 RING Signal Select Square wave Trapezoidal wave Sinusoidal wave
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D/625/2
ISDN TA POTS Interface
CMX625
1.5.12 Tx UART This block connects the IOM-2 serial bus interface to the FSK Encoder. The block can be programmed to convert transmit data from 8-bit bytes to asynchronous data characters by adding Start and Stop bits. The transmit data is then passed to the FSK Encoder. Data to be transmitted should be loaded, via the IOM-2 bus interface, into the TX DATA Register when the Tx Data Ready bit (bit 6) of the STATUS Register goes high. It will then be treated by the Tx UART block in one of two ways, depending on the setting of bit 1 of the SETUP Register: If bit 1 of the SETUP Register is `0' (Tx Sync mode) then the 8 bits from the TX DATA Register will be transmitted sequentially at 1200bps, lsb (D0) first. If bit 1 of the SETUP Register is `1' (Tx Async mode) then bits will be transmitted as asynchronous data characters at 1200 bps according to the following format: One Start bit (Space) Eight Data bits (D0-D7) from the TX DATA Register, with the lsb (D0) transmitted first One Stop bit (Mark) Failure to load the TX DATA Register with a new value when required will result in bit 7 (Tx Data Underflow) of the STATUS Register being set to `1'. If the `Tx Async' mode of operation is selected then a continuous Mark (`1') signal will be transmitted until a new value is loaded into TX DATA. If the `Tx Sync' mode is selected then the byte already in the TX DATA Register will be re-transmitted.
Figure 9a Transmit UART Function (Async)
Figure 9b Transmit UART Function (Sync)
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D/625/2
ISDN TA POTS Interface
CMX625
1.5.13 DTMF Tone Decoder This block is enabled or disabled by bit 5 of the SETUP Register. If disabled, bit 4 and 5 of the STATUS Register and bit 0 to bit 3 of the DTMF RX DATA Register are set to `0' and no interrupts are generated. When bit 5 of the SETUP Register is enabled and bit 4 of the INTERRUPT MASK Register is set to `1' (i.e. unmasked) a `detected tone' generates an interrupt and bit 4 of the STATUS Register is set to `1'. Reading the STATUS Register clears the IRQN output. When bit 5 of the SETUP Register is enabled and bit 5 of the INTERRUPT MASK Register is unmasked (logic `1'), a `status change' of the decoder will generate an interrupt and bit 5 of the STATUS Register will be set to `1'. The validity of the data is indicated by bit 4 of the STATUS Register. The decode truth table is shown below. Reading the STATUS Register clears the IRQN output. An interrupt is not generated when `no tone' is detected. DTMF RX DATA Register Bits 0 - 3 Bit 3 Bit 2 Bit 1 Bit 0 (D3) (D2) (D1) (D0) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 DTMF Tone Pairs Lower Frequency Upper Frequency (Hz) (Hz) 941 1633 697 1209 697 1336 697 1477 770 1209 770 1336 770 1477 852 1209 852 1336 852 1477 941 1336 941 1209 941 1477 697 1633 770 1633 852 1633
Keypad Legend D 1 2 3 4 5 6 7 8 9 0 * # A B C
A status change of the decoder and the generation of an interrupt (when the INTERRUPT MASK Register bit 5 is unmasked) will occur both when a tone is first decoded and also when a tone, which was previously present, is no longer decoded. In the latter case, bit 4 of the STATUS Register will be set to `0' to indicate that no tone was detected. The decoded tone pair is indicated by bits 0-3 in the DTMF RX DATA Register.
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D/625/2
ISDN TA POTS Interface
CMX625
1.5.14 Register Set Write Only Registers
Addr. $1 $3 Register RESET SETUP 7 N/A Tx Output Buffer 0=Disable 1=Enable SPM O/P: 0=Disable 1=Enable D7 MSB D7 MSB Codec Channel Select [1] Mask Status [7] 6 N/A Tx Enable 0=Disable 1=Enable Tone/FSK: 0=Disable 1=Enable D6 D6 Codec Channel Select [0] Mask Status [6] 5 N/A DTMF Rx: 0=Disable 1=Enable Tone/FSK: 0=Tone 1=FSK D5 D5 Data Byte Structure 4 3 N/A SPM: 0=12kHz 1=16kHz Tx Level: MSB D4 D3 Ring Signal Ring Signal Select [1] Select [0] Tx Level: Tx Level: LSB D2 N/A 2 N/A 1 N/A 0 N/A
FSK Mode: FSK Mode: 0=Sync 0=V23 1=Async 1=Bell 202 Tone Fields: Tone Fields: MSB D1 D1 C/I1 Channel Output Control [1] 0 LSB D0 LSB D0 LSB C/I1 Channel Output Control [0] 0
$4 $5 $6
MODE TX DATA TX TONES IOM CONTROL INTERRUPT MASK CODEC CONTROL
$8
$9
D4 D3 D2 LSB MSB IC Channel Remote Bus Reversal Digital IOM C/I1 0 0=Normal Loopback Channel 1=Reverse 0=No loopbk Output 1=Loopback Control [2] Mask Mask Mask Mask Status [5] Status [4] Status [3] Status [2]
$C
Codec Local Enable PCM Codec: Analogue 0=Disable 0=A-Law Loopback 1=Enable 1=-Law 0=No loopbk 1=Loopback
0
0
0
0
0
Read Only Registers
Addr. $0 $A Register DEVICE ID STATUS DTMF RX DATA 7 1 6 0 5 0 Data Byte Structure 4 3 1 DTMF Rx: 1=Detected 0=No Tone Time Out 0 1 IOM: Tx Abort DTMF: Rx Data (D3 MSB) 2 0 IOM: Rx Abort DTMF: Rx Data (D2) 1 0 0 DTMF: Rx Data (D1) 0 1 0 DTMF: Rx Data (D0 LSB)
FSK Mode: FSK Mode: DTMF Rx: FSK Tx Data FSK Tx Data Status Underflow Ready Change 0 0 0
$B
Notes: 1. Accessing the RESET Register clears all of the bits in the SETUP, MODE, TX DATA, TX TONES, IOM CONTROL, INTERRUPT MASK, CODEC CONTROL, STATUS and DTMF RX DATA registers and will initialise the device. This a single-byte transaction consisting of the address byte value $1. 2. If any of bits 2, 3, 4, 5, 6 or 7 of the STATUS Register is `1' then the IRQN output will be pulled low when the appropriate bit contains an unmasked logic `1' in the INTERRUPT MASK Register. 3. Reading the STATUS Register clears the IRQN output (when the appropriate bit contains an unmasked logic `1' in the INTERRUPT MASK Register) and also clears all the STATUS Register bits 2 to 7, if set. 1.5.15 Programming the CMX625
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D/625/2
ISDN TA POTS Interface
CMX625
The CMX625 is programmed via the `MON1' (Monitor Channel 1) channel in TE mode and the `Monitor' channel in non-TE mode. The programming sequence consists of 3 consecutive Monitor bytes: the IOM-2 address, the CMX625 command and data byte. Before executing a command, the CMX625 compares the received IOM-2 address byte with its own address. The MSB of the IOM-2 address is always a `1' (see section 1.5.2). A logical `1' in the MSB of the CMX625 command represents a write operation and a logical `0' represents a read operation. Structure for Register read/write operations: IOM Command Register R/W 0=Read 1=Write 0 X X Register Address A3 Register Address A2 Register Address A1 Register Address A0
Example 1: Program the CMX625 to generate interrupt requests for DTMF RX Status Change on bit 5 of C/I channel, i.e. C/I1 Channel Output Control Code (2-0)=110. Set IOM-2 address to SA2-SA0=010 and device select, DS=1.
MX (DD) MR (DU) DD (hex) MX (DU) MR (DD) DU (hex)
Comment Monitor Channel Idle State Transmit IOM-2 Address Acknowledge Address Transmit Command (Write IOM-2 Control, $8) Acknowledge Command/ Transmit IOM-2 Control Data Acknowledge Data End of Transmission Transmit IOM-2 Address Acknowledge Address Transmit Command (Write Mask Register, $9) Acknowledge Command/ Transmit IOM-2 Control Data Acknowledge Data End of Transmission Idle
1 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1 1
1 1 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1
FF A8 A8 88 88 06 06 FF FF A8 A8 89 89 20 20 FF FF FF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
If the command is a register read then only the address and command bytes are sent. The CMX625 will respond with an IOM-2 Register address byte followed by the read data. The IOM-2 Register address byte consists of the Register address that is being read in the least significant 4 bits and the IOM-2 address (less the device select bit) in the most significant 4 bits.
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D/625/2
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CMX625
Example 2: Read the CMX625 DTMF RX DATA register, D3-D0=$A. Set IOM-2 address to SA2-SA0 =100 and device select, DS=0.
MX (DD) MR (DU) DD (hex) MX (DU) MR (DD) DU (hex)
Comment Monitor Channel Idle State Transmit IOM-2 Address Acknowledge Address Transmit Command (Write IOM-2 Control, $B) Acknowledge Command/ Send Address Address Acknowledged Send DTMF Read Data Data Acknowledged End of Transmission Idle
1 0 0 1 0 1 1 1 1 1 1 1
1 1 0 0 1 0 1 1 1 1 1 1
FF C0 C0 0B 0B FF FF FF FF FF FF FF
1 1 1 1 1 0 0 1 0 1 1 1
1 1 1 1 1 1 0 0 1 0 1 1
FF FF FF FF FF CB CB 0A 0A FF FF FF
1.5.16 Glossary ADC CIDCW CODEC DAC DTMF FSK GCI IOM-2 ISDN ITU NTU PC PCM POTS SPM TA Analogue to Digital Converter Caller Identification During Call Waiting Coder/Decoder Digital to Analogue Converter Dual Tone Multiple Frequency Frequency Shift Keying General Circuit Interface ISDN Oriented Modular revision 2 Integrated Services Digital Network International Telecommunication Union Network Termination Unit Personal Computer Pulse Code Modulation Plain Old (Analogue) Telephone Service Subscriber Pulse Metering Terminal Adaptor
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D/625/2
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CMX625
1.6
Application Notes
When using the Tone/FSK bit (bit 6) of the MODE Register, each tone starts from VBIAS, and returns to VBIAS before ending:
Figure 10 Tone Starting and Stopping When switching between tones in the same column (bits 4 - 7 or bits 0 - 3) of the TX TONES Register), the transition will be phase continuous. However, switching to the `OFF' state will immediately take the output of that tone generator to VBIAS.
Figure 11 Tone Changing The TX TONES Register which does not have a frequency allocated is indicated by `-' in the Tone Field tables. These values should not be used.
1.6.1
Telecom Tones The following tables give the hex codes to be programmed into the particular tone field location for various telecommunications systems applications. The tables are not exhaustive, but list the more commonly used tones.
Ringing Signals (f 2.5%) (Hz) Off 16.7 20 25 35 40 50 Field 0 (Hex) $00 $01 $02 $03 $04 $05 $06
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CMX625
On Hook `CPE Alert Tones Single Tone (Hz) 375.2 404.3 468 495.8 520.6 548 562.8 578.4 1633 Field 0 (Hex) $60 $70 $80 $90 $A0 $B0 $C0 $D0 $0D Dual Tone (Hz) 375.2+1827 404.3+1827 468+1827 495.8+1827 520.6+1827 548+1827 562.8+1827 578.4+1827 Field 0 (Hex) $6E $7E $8E $9E $AE $BE $CE $DE
NYNEX (MRAA) - AMR Alert Tones (Single Tone) Group A (Hz) 252.4 268.7 285.3 315.5 330.5 375.2 Field 0 (Hex) $10 $20 $30 $40 $50 $60 Group B (Hz) 468 495.8 520.6 562.8 595 612.5 Field 0 (Hex) $80 $90 $A0 $C0 $E0 $F0
Single Frequency Call Progress Tones (Hz) Off 120 150 154 250 300 350 400 425 440 450 480 500 600 620 Field 1 (Hex) $00 $10 $20 $30 $40 $50 $60 $C0 $04 $06 $07 $09 $0A $0B $0C
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D/625/2
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CMX625
Dual Frequency Call Progress Tones Additive Mixing (Hz) Off 350+440 440+480 480+620 400+425 400+450 425+450 425+480 120+620 150+450 Field 1 (Hex) $00 $66 $F6 $FC $C4 $C7 $D4 $F4 $1C $27
Multiplicative
Mixing (Hz) 400*16.2 400*20 400*25 400*33 400*40 400*50 450*25 600*120
Field 1 (Hex) $B2 $A3 $94 $85 $76 $67 $E4 $FD
Dual Tone Multi Frequency Generation Field 2 (Hex) $00 $FF $CC $CD $CE $DC $DD $DE $EC $ED $EE $FD $FC $FE $CF $DF $EF
(Hz) Off 941+1633 697+1209 697+1336 697+1477 770+1209 770+1336 770+1477 852+1209 852+1336 852+1477 941+1336 941+1209 941+1477 697+1633 770+1633 852+1633
Special Information Tones, Fax and Modem Tones and Customer Premises Alert Tones Field 2 (Hex) $00 $80 $30 $40 $90 $A0 $08 $09 $BB
(Hz) Off 950 1100 1300 1400 1800 2100 2225 2130+2750
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CMX625
ITU-T `R1' Signalling Tones (Hz) 700+900 700+1100 900+1100 700+1300 900+1300 1100+1300 700+1500 900+1500 1100+1500 1300+1500 700+1700 900+1700 1100+1700 1300+1700 1500+1700 Field 2 (Hex) $12 $13 $23 $14 $24 $34 $15 $25 $35 $45 $16 $26 $36 $46 $56
ITU-T `R2' Signalling Tones Forward mode (Hz) Off 1380+1500 1380+1620 1500+1620 1380+1740 1500+1740 1620+1740 1380+1860 1500+1860 1620+1860 1740+1860 1380+1980 1500+1980 1620+1980 1740+1980 1860+1980 Field 3 (Hex) $00 $89 $8A $9A $8B $9B $AB $8C $9C $AC $BC $8D $9D $AD $BD $CD Backward mode (Hz) Off 1140+1020 1140+900 1020+900 1140+780 1020+780 900+780 1140+660 1020+660 900+660 780+660 1140+540 1020+540 900+540 780+540 660+540 Field 3 (Hex) $00 $65 $64 $54 $63 $53 $43 $62 $52 $42 $32 $61 $51 $41 $31 $21
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D/625/2
ISDN TA POTS Interface
CMX625
1.7
1.7.1
Performance Specification
Electrical Performance
1.7.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. -0.3 -0.3 -50 -20 Min. -55 -40 Min. -55 -40 Max. 7.0 VDD + 0.3 +50 +20 Max. 550 9 +125 +85 Max. 800 13 +125 +85 Unit V V mA mA Unit mW mW/C C C Unit mW mW/C C C
Supply (VDD - VSS) Voltage on any pin to VSS Current into or out of VDD and VSS pins Current into or out of any other pin D5 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature P4 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature
1.7.1.2 Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) Operating Temperature Min. 2.7 -40 Max. 5.5 +85 Unit V C
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D/625/2
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CMX625
1.7.1.3 Operating Characteristics For the following conditions unless otherwise specified: VDD = 2.7V at Tamb = 25C and VDD = 3.0V to 5.5V at Tamb = -40 to +85C, 0dBm = 775mVrms = 0dBm0. DC Parameters IDD All Enabled, VDD = 5.0V All Disabled, VDD = 5.0V DTMF Rx only, VDD = 5.0V Tx (tones, SPM) only, VDD = 5.0V Tx Output Buffer only Enabled, VDD = 5.0V PCM Codec only, VDD = 5.0V All Enabled, VDD = 3.3V All Disabled, VDD = 3.3V DTMF Rx only, VDD = 3.3V Tx (tones, SPM) only, VDD = 3.3V Tx Output Buffer only Enabled, VDD = 3.3V PCM Codec only, VDD = 3.3V Logic `1' Input Level (CMOS inputs) Logic `0' Input Level (CMOS inputs) Logic Input Leakage Current (Vin = 0 to VDD) Logic `1' Input Level (TTL inputs) Logic `0' Input Level (TTL inputs), Vdd = 3.3V-5.5V Output Logic `1' Level DD, DU (IOH = 4mA) Output Logic `0' Level DD DU (IOL = 6mA) Output Logic `0' Level IRQN (IOL = 3mA) IRQN O/P `Off State Current (VOUT = VDD) FSK Encoder and Tx UART Level at TONEFSK pin Twist (Mark level w.r.t. Space level) Tx 1200bits/sec (V23 mode) Baud Rate (set by UART and DCL) Mark (Logical 1) Frequency Space (Logical 0) Frequency Tx 1200bits/sec (Bell 202 mode) Baud Rate (set by UART and DCL) Mark (Logical 1) Frequency Space (Logical 0) Frequency TONEFSK Signal Level Level at TONEFSK pin for: Single tone Dual tone (per tone) DTMF High Frequency Group DTMF Low Frequency Group Output Impedance Tone frequency resolution Tone output distortion Notes 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3, 13 14 14 14 Min. 70% -1.0 2.0 0.8 Min. -1.0 -2.0 1194 1297 2097 1194 1197 2197 Notes 4 4 4 4 5 Min. -1.0 -4.0 -4.0 -6.0 -2.5 Typ. 6.9 140 2.4 3.5 1.8 3.1 5.0 80 1.6 2.3 1.3 2.3 Typ. 0 0 1200 1300 2100 1200 1200 2200 Typ. 0 -3.0 -3.0 -5.0 10.0 0.8 Max. 30% +1.0 0.8 0.4 0.4 1.0 Max. 1.0 +2.0 1206 1303 2103 1206 1203 2203 Max. 1.0 -2.0 -2.0 -4.0 2.5 Unit mA A mA mA mA mA mA A mA mA mA mA V V A V V VDD V V A Unit dBm dB Baud Hz Hz Baud Hz Hz Unit dBm dBm dBm dBm k Hz %
Notes 4
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D/625/2
ISDN TA POTS Interface
CMX625
DTMF Decoder Valid input signal levels (each tone of composite signal) Not decode level (either tone of composite signal) Twist = High Tone/Low Tone Frequency Detect Bandwidth Dial Tone Tolerance Noise Tolerance Tone Response time Tone De-response time Tone burst detected Tone burst ignored Pause length detected Pause length ignored SPM Signal Level Level at SPM pin Tone frequency accuracy Tone output distortion Output Impedance PCM Codec-Filter PCM Codec-Filter Passband Passband Gain (at 1.02kHz) Passband Ripple (w.r.t. gain at 1.02kHz) Stopband Attenuation Group delay Absolute Relative to 1kHz: 500Hz 600Hz 2600Hz 2800Hz Signal-to-total distortion ratio as a function of input level (1kHz input level): -45dBm -40dBm -30dBm 0dBm Variation of gain with input level (1kHz input signal) -55dBm0 -50dBm0 -40dBm0 +3dBm0 Idle channel noise Output Impedance
Notes 4 4 6 6,7 2 2 2 2 2 2 Notes 4, 9 4, 9, 10 5
Min. -29.0 -9.0 1.8 40.0 40.0 Min. -1.5 -1.0 -14.0 Min. 300 -0.5 -
Typ. -14 20.0 Typ. 0 0 1.2 10.0 Typ. 0 30.0 1.0
Max. -2.0 -40.0 10.0 4.5 0 40.0 45.0 20.0 Max. 1.0 0.5 14.0 Max. 3400 +0.5 600 1.5 0.75 0.25 1.5 +3.0 +1.0 +0.5 +0.5 -65.0 -
Unit dBm dBm dB % dB dB ms ms ms ms ms ms Unit dBm dB Hz % k Unit Hz dB dB dB s ms ms ms ms dBp dBp dBp dBp dB dB dB dB dBm0p k
Notes 8 8 8 8
11 11 11 11
22.0 27.0 33.0 33.0 -3.0 -1.0 -0.5 -0.5 -
11
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D/625/2
ISDN TA POTS Interface
CMX625
Tx Output Buffer Buffer output signal swing; Load greater than 500 Power-Up Timing Device reset to reliable signal at TXO, TXON, RING, SPM or TONEFSK output pins Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
Notes 12
Min. 2.2
Typ. -
Max. -
Unit Vp-p
Notes
Min. -
Typ. 50.0
Max. -
Unit ms
At 25C, not including any current drawn from the CMX625 pins by external circuitry. At nominal signal frequencies and without skew. Excluding IOM-2 serial bus interface pins: FSC, DCL, DD and DU in bus reversal. At VDD = 5.0V, load resistance greater than 40k, signal levels are proportional to VDD. Frequency above 300Hz. Referenced to DTMF tone of lower amplitude. Bandwidth limited: 0 to 3.4kHz Gaussian Noise. See filter response, Figure 12. SPM has a soft rise and fall time of about 4ms. The level changes between VBIAS and 0dBm in 2dB steps, 16 steps per rise and fall. When SPM is disabled, an extra 4ms falling tail end of signal should be taken into consideration. Over the range VDD = 3.3V to 5.5V at Tamb = 25C. Represents a psophometrically weighted measurement. For each of the TXON (if enabled) and TXO pins, load placed between the pin and VDD / 2, for VDD = 5.0V only. Derate linearly minimum TTL Logic `0' level from 0.8V at Vdd = 3.3V to 0.5V at Vdd = 2.7V. All outputs CMOS levels.
2001 Consumer Microcircuits Limited
30
D/625/2
ISDN TA POTS Interface
CMX625
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 0 500 1000 1500 2000 2500 3000 3500 Frequency (Hz)
Figure 12a Passband - PCM Codec-Filter overall frequency response
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 1000 2000 3000 4000 Frequency (Hz) 5000 6000 7000 8000
Gain (dB)
Figure 12b PCM Codec-Filter overall frequency response
2001 Consumer Microcircuits Limited
31
D/625/2
ISDN TA POTS Interface
CMX625
IOM-2 Bus Timing (See Figure 13) tDCL tDCL tR / tF FSC tFSCS tFSCH tDUDC tDUDF Notes: DCL clock period in TE Mode DCL clock period in non-TE Mode DCL clock rise time / fall time FSC period FSC set-up time FSC hold time DU delay clock (data out) DU delay frame (data out)
Notes 1 1 1 1 1 1 2 2
Min. 70 40 -
Typ. 651 244 125 -
Max. 60 100 150
Unit ns ns ns s ns ns ns ns
1. These signals are requirements and are not under control of CMX625. 2. Condition CL = 150pF.
Figure 13 IOM-2 Bus Timing Diagram
Typical UART Timings (See Figures 9a and 9b) TFSK TDLY TDRDY TUFL (delay through the modulator) (1 bit period) (1/4 bit-period) (3/4 bit-period)
Notes
Min. -
Typ. 106 833 208 625
Max. -
Unit s s s s
2001 Consumer Microcircuits Limited
32
D/625/2
ISDN TA POTS Interface
CMX625
1.7.2
Packaging
Figure 12 24-pin SSOP (D5) Mechanical Outline: Order as part no. CMX625D5
Figure 13 24-pin DIL (P4) Mechanical Outline: Order as part no. CMX625P4
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.
Oval Park - LANGFORD MALDON - ESSEX CM9 6WG - ENGLAND
Telephone: +44 (0)1621 875500 Telefax: +44 (0)1621 875600 e-mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/1 February 2002

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